1. Technical Field
Example embodiments of the present invention relate to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including a through via, and a method of manufacturing the same.
2. Related Art
Recently, in semiconductor devices, with reduction of chip sizes and increase of the number of input-and-output terminals due to miniaturization process techniques and diversification of functions, pitches of electrode pads are gradually reduced, convergence of various functions is accelerated, and thus a system-level packaging technique in which various devices are integrated in a single package has emerged. In addition, the system-level packaging technique is being changed to a three-dimensional (3D) stacking technique in which a short signal distance can be maintained in order to minimize noise between operations and improve a signaling rate.
Meanwhile, in addition to such a demand for technical improvement, in order to control product costs, increase productivity, and reduce manufacturing costs, a semiconductor package formed by stacking a plurality of semiconductor chips is being introduced. For example, a multi-chip package (MCP) in which a plurality of semiconductor chips are stacked in a single semiconductor package and a system in package (SiP) in which different types of stacked chips operate as a single system are being implemented.
The SiP, which is a package for modularizing high density integrated circuits (ICs) such as semiconductor dies, is applied to portable terminals in which it is difficult to secure a mounting space, but is being variously applied to other products in recent years.
In this way, recently, a semiconductor package has been gradually miniaturizing, and a thickness thereof has also been decreasing.
However, in a package-on-package (PoP) in the related art, there is a limit in slimming a semiconductor package, and it is difficult to satisfy a fine pitch due to miniaturization.